Chiplets: How Modular Silicon Is Building a USD 126.6 Billion Market
Executive summary. A chiplet is a small piece of silicon that does one job, such as computing, memory, input and output or networking, and is combined with other chiplets in one package to act as a single processor. For decades chipmakers improved performance by shrinking transistors on one large die. That is getting slower and more expensive, so the industry is building processors like Lego: mixing chiplets made on different processes and from different suppliers. AI accelerators and data center processors have made this the default design approach. Strategic Revenue Insights estimates the global chiplet market at USD 8.5 billion in 2025, rising to USD 126.6 billion by 2034 at a 35.00 percent compound annual growth rate. Slowing transistor scaling, high-bandwidth memory integration, packaging capacity constraints and demand for AI and high-performance computing are driving it. This article sets out five lessons from the chip designers, foundries and packaging specialists moving first, with takeaways for strategy, product, operations, channels and revenue.
The structure of the market shows where value is concentrating. Strategic Revenue Insights' Chiplet Market research finds that compute chiplets, including CPUs, GPUs and NPUs, are the largest segment, that memory chiplets and HBM stacks are the fastest growing, and that Asia Pacific is both the largest and the fastest growing region. The research names rising manufacturing complexity and cost, rapid technology change and intellectual property disputes as challenges, and lists AMD, Intel, TSMC, Marvell, Broadcom, Samsung Electronics, Arm, Alphawave Semi, Eliyan and Ayar Labs among the key companies.
Open standards are making chiplets from different suppliers easier to combine. The UCIe Consortium released its Universal Chiplet Interconnect Express 3.0 specification in August 2025, supporting data rates of up to 64 GT/s, double the previous version, according to the consortium.
Why the Chiplet Market Is Entering a New Phase
Three structural forces are converging.
Monolithic chips are hitting limits. SRI's research notes that slowing transistor scaling shifts performance gains toward advanced packaging and heterogeneous integration. Large single dies are costly to make and yield poorly.
AI needs memory next to compute. AI accelerators combine compute chiplets with stacks of high-bandwidth memory on one package. SRI's research identifies memory chiplets and HBM stacks as the fastest growing segment, a trend explored in how AI is turning HBM into a strategic market.
Packaging is the new bottleneck. SRI's research notes that packaging capacity has become a bottleneck separate from front-end wafer supply, and that thermal and power delivery needs raise substrate and material requirements. The heat challenge links to why liquid cooling is taking over AI data centers.
These forces explain SRI's forecast of very rapid growth to 2034, with value concentrating in compute and memory chiplets, advanced packaging and Asia Pacific.
Five Lessons From the Companies Moving First
The chip designers and packaging specialists turning these forces into advantage share a recognisable pattern. We have distilled it into five lessons, each followed by a takeaway for a specific leadership function.
Lesson 1: Design the Product as a Platform
The companies moving first design processor families as platforms of reusable chiplets. One compute die can be combined with different numbers of memory, input-output and accelerator chiplets to create products for laptops, servers and AI clusters. AMD's chiplet-based processors showed how this cuts cost and time to market.
"With chiplets, a chip company stops designing one product at a time and starts building a kit it can reconfigure for every market."
Takeaway on strategy. Design processor families as platforms of reusable chiplets, and plan product ranges by combining a small set of dies in different ways.
Lesson 2: Put Each Function on the Right Process
Not every part of a chip needs the most advanced and expensive manufacturing process. The companies moving first put compute on the newest node, keep input-output, analogue and memory interfaces on older and cheaper nodes, and buy specialised chiplets, such as optical or networking dies, from partners. SRI's research names new chiplet combinations enabled by heterogeneous integration as an opportunity.
Takeaway on product. Place each function on the most cost-effective process, buy specialised chiplets where partners lead, and design for heterogeneous integration from the start.
Lesson 3: Secure Packaging Capacity Early
Advanced packaging, including silicon interposers and stacked dies, is in short supply. SRI's research identifies packaging capacity as a bottleneck separate from wafer supply. The companies moving first reserve packaging capacity years ahead, qualify more than one packaging partner and invest in thermal and power delivery engineering.
"In the chiplet era, a reserved slot on an advanced packaging line can be worth as much as a wafer allocation."
Takeaway on operations. Reserve advanced packaging capacity early, qualify several packaging partners, and invest in thermal, power delivery and test engineering.
Lesson 4: Bet on Open Interconnects and Ecosystems
Chiplets from different companies only work together if they share standards. UCIe and related efforts define how dies talk to each other. SRI's research names advanced interconnect technologies as an opportunity and intellectual property disputes as a challenge.
The companies moving first adopt open standards, join ecosystems of chiplet suppliers and offer their own dies to others. Specialists such as Alphawave Semi, Eliyan and Ayar Labs focus on the interconnect layer, including optical links similar to those in why 800G optical transceivers are scaling with AI.
Takeaway on channels. Adopt open interconnect standards, join chiplet ecosystems, and offer interoperable dies and interconnect IP to partners.
Lesson 5: Asia Pacific Builds and Grows Fastest
SRI's research identifies Asia Pacific as both the largest and the fastest growing region. Taiwan hosts the leading foundry and advanced packaging capacity, South Korea leads in memory, and China, Japan and Southeast Asia are expanding packaging and test. North America remains the centre of chip design. SRI's research also notes that export rules on advanced computing chips shape product roadmaps.
The capabilities that decide who captures this demand are specific:
Platform designs built from reusable chiplets.
Cost-optimised use of process nodes and partner dies.
Reserved advanced packaging and thermal engineering.
Open interconnects and ecosystem partnerships.
Supply chains spread across Asia Pacific and compliant with export rules.
Companies evaluating these competitive dynamics in greater detail can use SRI's Chiplet Market analysis to assess chiplet type, application and region segments and the positioning of the leading suppliers.
Takeaway on market development. Keep close ties with Asian foundry, memory and packaging partners, diversify packaging locations, and design product variants that meet export control tiers.
Where the Opportunity Is Concentrating
Value is moving toward compute and memory chiplets, advanced packaging and interconnects.
By type, compute chiplets are the largest and memory chiplets and HBM stacks grow fastest.
By application, data centers and AI accelerators lead, with automotive and networking expanding.
By geography, Asia Pacific is the largest and fastest growing region.
At the Horizon: What to Watch Over the Next Three Years
Multi-vendor chiplet products. The first processors combining chiplets from different companies will test open standards.
Packaging capacity. Expansion of advanced packaging lines will decide how fast AI chip supply can grow.
Export controls. Changes in rules on advanced chips will shape product designs and markets.
"The next phase of chips will be won by the companies that combine the best dies from anywhere into one package that performs as a single system."
The Strategic Revenue Opportunity
For chip designers, the task is to build reusable chiplet platforms. For foundries and packaging specialists, the opportunity lies in advanced packaging capacity and services. For interconnect and IP companies, the priority is standards-based dies and links. For investors, the signal is packaging capacity, design wins and ecosystem adoption.
Market intelligence turns these questions into decisions. Segment-level analysis shows where chiplet type and application demand is concentrating, competitive analysis shows how suppliers are positioned, and regional analysis shows where capacity and demand will grow. This is the path from market signals to strategic insight to revenue impact.
Takeaway on revenue. Treat the chiplet market as four revenue pools: compute chiplets sold in processors, memory and HBM stacks sold to accelerator makers, packaging and test services sold to designers, and interconnect IP and specialised dies sold to ecosystems. Each needs its own pricing model.
The Next Leg: Preparing for the Journey Ahead
The defining shift in semiconductors is that performance now comes from how chips are combined, not only how small transistors become. That changes how processors are designed, made and sold. The companies moving first are not the ones with the largest dies; they are the ones building platforms, placing functions wisely, securing packaging, embracing open interconnects and building where capacity is concentrated.
The next three years will decide which companies become the default suppliers of modular silicon for AI and computing. Decision-makers should invest in chiplet platforms, packaging and ecosystems and track multi-vendor products, packaging capacity and export rules. Companies evaluating growth opportunities in this market can use Strategic Revenue Insights' Chiplet Market report to assess market size, competitive dynamics, regional opportunities and strategic growth priorities.
Sources: Strategic Revenue Insights, Chiplet Market report (2026); UCIe Consortium, UCIe 3.0 specification announcement (August 2025).
Frequently Asked Questions
How big is the chiplet market?
Strategic Revenue Insights estimates the global chiplet market at USD 8.5 billion in 2025, rising to USD 126.6 billion by 2034 at a 35.00 percent compound annual growth rate. Compute chiplets are the largest segment, and Asia Pacific is the largest and fastest growing region.
What is driving growth in chiplets?
Slowing transistor scaling, integration of high-bandwidth memory for accelerated computing, packaging capacity constraints, rising thermal and power requirements and demand for AI and high-performance computing are the main drivers of chiplet growth, according to Strategic Revenue Insights.
What is UCIe?
Universal Chiplet Interconnect Express, or UCIe, is an open standard for connecting chiplets from different suppliers in one package. The UCIe Consortium released version 3.0 in August 2025, supporting data rates of up to 64 GT/s, double the previous version.
Which chiplet segment is growing fastest?
Memory chiplets and HBM stacks are the fastest growing segment, according to Strategic Revenue Insights, driven by AI accelerators that place high-bandwidth memory next to compute chiplets. Compute chiplets, including CPUs, GPUs and NPUs, remain the largest segment.
About the authors: This article was prepared by the Strategic Revenue Insights research team, which combines market intelligence, competitive analysis and strategic advisory for growth-stage, mid-market and enterprise organisations across the ICT, semiconductor and electronics sector.
Sector analyst: Lukas Schmidt, Technology and Infrastructure Analyst. Our market estimates combine primary research (interviews, surveys and expert panels) with secondary data (industry reports, databases and public disclosures); read more about how Strategic Revenue Insights works. To discuss this market with our analysts, contact our team.
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